Prof. Re-Ching Lin, FCU
Speech Title: Development, Market Trends, and Challenges of RF Front-End Technology
- Engineer, Optoelectronics & Systems Laboratories, ITRI
- Deputy Manager, R&D Department, WIN Semiconductors Corp.
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Co-founder & General Manager, Grandeur Microelectronics
The development of RF front-end technology is a key driver in the evolution of communication systems. As future communication systems demand increasingly high performance, the requirements for various RF front-end components must be correspondingly enhanced. In addition, the miniaturization of RF front-end modules in smartphones and wearable devices has become a critical requirement, drawing significant attention to integration technologies. However, the industry also faces intense market competition and numerous challenges. Overcoming technical difficulties while maintaining a competitive market position remains a major challenge for the RF front-end industry.
Prof. Ying-Chao Hsu, National Taipei University of Technology
Speech Title: Heterogeneous Integration trend and technology challenges
Ph.D. of Materials Science and Engineering In National YangMin- ChiaoTung University.
- Taiwan Semiconductor Manufacturing Corporation
Principle engineer: Backend of line (BEOL) etch module, R&D dept.
28nm BEOL metal hard mask and low K dual damascene etch process development. Yield & reliability enhancement - Lam Research Corporation
Technical manager: Field process department
Fab yield for new tech. transfer, yield ramp up, pi-line start up, advance etch process development in DRAM 20nm, 1x, 1y , 1z tech. node.
Co-develop with PSMC, MXIC and Nanya RD teams for 3DIC etch, deposition and wet process. - National Taipei University of Technology
Assistant professor in Institute of materials science and engineering.
Research focus: Heterogeneous integration, low temp. hybrid bonding
2.5D packaging connects different chips through a silicon interposer, and 3D packaging uses TSV + micro-bump technology to connect vertically stacked chips. Heterogeneous integration is enabling high-end applications (AI, mobile/5G, AR/VR, automotive, etc.).
System-on-Integrated-Chips (SoIC) can bridge the gap between chips through micro-bump connections to the silicon interposer for signal transduction. Due to the difficulty of shrinking the micro-bump pitch, SoIC will use copper-to-copper and dielectric layer-to-dielectric layer bonding technology (hybrid bonding) to replace traditional bumps to increase interconnect density, reduce pitch, chip thickness, and shorten signal transmission distance.
High-temperature hybrid bonding can easily decrease device reliability. The industry requires lowering the bonding temperature to reduce the impact on device reliability.