Yong-Jay Lee, Bryan, ITRI/MCL,
Dept. of Metal-Organic Materials Synthesis and Advanced-Deposition Process
Speech Title: Challenges in the Synthesis of ALD Precursors
Education:
M.S. in Chemistry, National Taiwan University
B.S. in Chemical Engineering and Material Engineering, National Central University
Experience:
Research Associate, Department of Chemistry, National Taiwan University
Research Assistant, Department of Chemistry, National Taiwan University
Current Position:
Manager, Dept. of Metal-Organic Materials Synthesis and Advanced-Deposition Process, MCL, ITRI
Downscaling the size of the transistors is the most critical part of maximizing the microchips' efficiency. However, as the size becomes smaller, the process becomes more difficult.
Fortunately, scientists invented the atomic layer deposition (ALD) process to introduce a high-quality coating to delicate chips, a process that works well in bigger chips.
However, synthesizing suitable precursors presents challenges due to the need for specific properties like high reactivity, thermal stability, and volatility, which are often difficult to achieve simultaneously.
This makes the research in ALD precursors worthy.
Prof. Tseung-Yuen Tseng, NCTU
Speech Title: Hafnium Zirconium Oxide Based Ferroelectric Tunnel Junctions for Neuromorphic Computing Applications
Prof. Tseung-Yuen Tseng received his Ph.D. degree in electroceramics from the School of Materials Engineering, Purdue University, West Lafayette, USA. He is now a Lifetime Chair Professor in the Institute of Electronics, National Yang Ming Chiao Tung University.
Dr. Tseng’s professional interests are electronic ceramics, nanoceramics, ceramic sensors, high-k dielectric films, ferroelectric thin films and their based devices, energy materials and resistive switching memory devices. He has published over 460 research papers in refereed international journals and 180 conference papers, several book chapters, and held 36 patents. He invented the base metal multilayer ceramic capacitors, which have become large scale commercial product. He was an Editor of the Handbook of Nanoceramics and Their Based Nanodevices(5-Vol. set) and Nonvolatile Memories: Materials, Devices, and Applications(2-Vol. set), Guest Editor of a special issue of Ferroelectrics(6 Vol. set), an Associate Editor of the Journal of Nanoscience and Nanotechnology and International Journal of Applied Ceramic Technology.
He was Chair of the Board of Asian Ferroelectrics Association and General Chair of The 6th Asian Meeting of Ferroelectrics. He has received Distinguished Research Award from the National Science Council (1995-2001), Hou Chin-Tui Distinguished Honor Award (2002), Dr. Sun Yat-Sen Academic Award (2003), TECO Technology Award (2004), IEEE CPMT Exceptional Technical Achievement Award (2005), Distinguished Research Award of Pan Wen Yuan Foundation (2006) , Academic Award of Ministry of Education (2006), Medal of Chih-Hung Lu(2010), National Endowed Chair Professor(2011), IEEE CPMT Outstanding Sustained Technical Contribution Award(2012), and Distinguished Achievement Award of the Phi Tau Phi Scholastic Honor Society(2018), Lifetime World’s Top 2% Scientists 1960-2023, Lifetime Achievement Award , IEEE, ROC section(2023), and Top Electronics and Electrical Engineering Scientists(Https://research.com/scientists-rankings/electronics-and-electrical engineering). He was elected a Fellow of the American Ceramic Society, IEEE Fellow ,MRS-T Fellow , APAM Academician and IEEE Life Fellow.
This talk will present that the ferroelectric tunnel junctions have high potential for nuromorphic application. Synapse plays an important role in learning and memory. It is the fundamental element for neuromorphic architecture. The working principle of the synapse and the synaptic features including potentiation and depression, Hopfield and convolutional neural network simulations, and spike timing-dependent plasticity will be briefly introduced.
In this work, we fabricate a ferroelectric tunnel junction (FTJ) device with W/MgO/HZO/TiN structure. The effect of MgO thickness on the FTJ properties of HZO films is studied. Device with 0.5 nm thick MgO insulating layer and annealing at 600 ℃ for 20 s exhibits a large memory window of about 30 and stable endurance of at least one million cycles with multilevel states. For pulse measurements, this device shows excellent nonlinearities of 0.1 and 0.32 for potentiation(P) and depression(D), respectively. The conductance data of P and D are input into simulated Hopfield neural network model for training to learn 10 × 10-pixel size images. Such model recognizes the input images to reach an accuracy of 100 % in only 19 iterations.
We also fabricate W/AlN/HZO/TiN structure devices as ferroelectric tunnel junctions (FTJs). After determining the suitable thickness of the ferroelectric layer HZO and annealing temperature, different annealing atmospheres and forming gas ambient are used to control the quantity of oxygen vacancies within HZO, aiming to achieve optimal device characteristics. Even after undergoing 106 pulses and 1000 s duration, respectively, the annealed device still maintains a memory window greater than one order. Neural characteristics are realized by the FTJ device, resembling artificial synapse.
Above results demonstrate that our FTJ devices have high potential working as artificial synapse for the neuromorphic computing application in the future.
In-Gann Chen, NCKU
Dept. of Materials Science and Engineering, National Cheng Kung University
Speech Title: Application and Prospects of Ceramic Abrasives in Semiconductor Chhemical Mechanical Planarization Process
Research Expertise：
Development and applications of high-temperature superconducting materials
Processing techniques for optoelectronics and nano-materials
Carbothermic Reduction of Iron Ore
Education：
Ph.D., Ohio State University, USA
M.S., University of Alabama, USA
B.S., National Cheng Kung University, Taiwan
Experience：
俄亥俄大學冶金工程博士(美國)
阿拉巴馬大學冶金工程碩士(美國)
國立成功大學冶金及材料工程學士(中華民國)
Chemical mechanical planarization (CMP) is a key process in semiconductor manufacturing, ensuring that wafer surfaces are perfectly flat and without defects before subsequent device processing. CMP relies on a combination of chemical reactions and mechanical abrasion—where the latter is critically governed by the nature of the abrasive particles in the slurry—to achieve the ultra-smooth surfaces required for advanced integrated circuits fabrication. A typical 7nm node wafer will require about 30 or more CMP steps using different types of slurries and processing chemicals.
The different sizes, shapes, and chemical stabilities of abrasive particles in CMP slurries directly affect the material removal rate (MRR) and defect rate on the wafer surface. We will discuss the types of ceramics abrasives used for Si and emerging wide bandgap semiconductors such as SiC and GaN. Additionally, this presentation will describe methods for characterizing ceramic particles in CMP slurries, including conventional dynamic light scattering (DLS) and advanced liquid cell TEM (LCTEM) techniques. It is believed that further development in this direction, integrated metrology, could provide tighter control over the formation of surface defects through precisely engineered aggregation and dispersion stability of nanoparticles in CMP slurries.